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Glossary VHDL / Term

designator

  1. Syntax that forms part of an association element. A formal designator specifies which formal parameter, port, or generic (or which subelement or slice of a parameter, port, or generic) is to be associated with an actual by the given association element. An actual designator specifies which actual expression, signal, or variable is to be associated with a formal (or subelement or subelements of a formal). An actual designator may also specify that the formal in the given association element is to be left unassociated (with an actual designator of open).
  2. An identifier, character literal, or operator symbol that defines an alias for some other name.
  3. A simple name that denotes a predefined or user-defined attribute in an attribute name, or a user-defined attribute in an attribute specification.
  4. An simple name, character literal, or operator symbol, and possibly a signature, that denotes a named entity in the entity name list of an attribute specification.
  5. An identifier or operator symbol that defines the name of a subprogram.

Permanent link designator - Creation date 2021-04-03


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