Glossary VHDL / Term
The building of a simulateable model through the top-down binding of its structural hierarchy, according to the configuration selected.
The process by which a declaration achieves its effect. Prior to the completion of its elaboration (including before the elaboration), a declaration is not yet elaborated.
Permanent link Elaboration - Modification date 2021-09-14 - Creation date 2021-06-13