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Glossary VHDL / Term

overloaded

Identifiers or enumeration literals that denote two different name entities. Enumeration literals, subprograms, and predefined operators may be overloaded. At any place where an overloaded enumeration literal occurs in the text of a program, the type of the enumeration literal must be determinable from the context.

Permanent link overloaded - Creation date 2021-04-03


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