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Glossary VHDL / Term

postponed process

An explicit or implicit process whose source statement contains the reserved word postponed. When a postponed process is resumed, it does not execute until the final simulation cycle at the current modeled time. Thus, a postponed process accesses the values of signals that are the “stable” values at the current simulated time.

Permanent link postponed process - Creation date 2021-04-03


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