Glossary VHDL / Term
An expression that converts the value of a subexpression from one type to the designated type of the type conversion. Associations in the form of a type conversion are also allowed. These associations have functions and restrictions similar to conversion functions but can be used in places where conversion functions cannot. In both cases (expressions and associations), the converted type must be closely related to the designated type. See also conversion function and closely related types.
Permanent link type conversion - Creation date 2021-04-03