Glossaria.net

Glossary VHDL / Term

delta cycle

A simulation cycle in which the simulation time at the beginning of the cycle is the same as at the end of the cycle. That is, simulation time is not advanced in a delta cycle. Only nonpostponed processes can be executed during a delta cycle.

Permanent link delta cycle - Creation date 2021-04-03


< deferred constant Glossary / VHDL denote >